Currently, the semiconductor industry is continuing to develop and implement smaller technology nodes, enabling a host of new and more powerful applications. However, as technology sizes continue to decrease, interconnect, i.e. wiring layers joining elements of a semiconductor device, is becoming a main design constraint and dominate in terms of system power consumption and performance due to its poor scaling capabilities. As shown in [D. Liu, C. Svensson, Power consumption estimation in CMOS VLSI chips, IEEE J. Solid-State Circuits, vol. 29, no. 6, pp. 663–670, June 1994], interconnects consume a significant fraction of total circuit power. Moreover, global wire length, is becoming a major hindrance, since its relative delay to the gate delay deteriorates as technology continues to shrink. Hence, wire buffer insertion has become popular [J. Cong, A interconnect-centric design flow for nanometer technologies, Proc. IEEE, vol. 89, no. 4, pp. 505–528, April 2001.]. However, this in turn has increased the portion of circuit power consumed by communication resources.
The memory communication network consists of a number of long wires. As a result its power consumption is becoming significant. The physical design plays an important role in power efficiency because the design determines the final wire length. Once the network influences the chip power consumption, the physical design should play an important role in power efficiency. As the first step of the physical design, floorplanning decides the relative position of the modules, so it is determining the interconnection cost to a large extent.
With the increasing of complexity of the VLSI chip, the physical design time also becomes longer. To get a layout in reasonable time, hierarchical floorplanning can contribute by cutting the solution space into smaller ones. In data dominated applications, the distributed memory organization distributes the application data into smaller memories, hence reduces the energy per access of each data elements [L. benini, L. Macchiarulo, A. Macii, M. Poncino, Layout driven memory synthesis for embedded Systems-on-Chip, IEEE Trans. on VLSI sysystems, vol. 10, no.2, April 2002]. However, more smaller memories means more blocks and more interconnections among the blocks. Hierarchical floorplanning is a good and fast solution to get the layout of the chip with a small overhead in power and delay. Another advantage is that it enables hard-IP reuse, which makes it very useful for incremental designs.
Most floorplanning strategies consider chip area and total wirelength as the optimization criteria. Although the interconnection cost has been paid more attention to, the activation frequencies of the wires are rarely taken into account at the physical design stage. However, in order to minimize the energy consumption of the communication network, the wire length of the most active wires has to be minimized.
In U.S. Pat. No. 6,668,337 B2 a method for designing integrated circuits based on a transaction analysing model is disclosed, wherein floorplanning steps are performed, in a context of power consumption optimisation.